1. Field of the Invention
The present invention relates to an electrically rewritable non-volatile memory device, and more specifically to an erroneous operation preventing circuit of a non-volatile memory device for setting one operational mode of a plurality of operational modes including at least a first reading mode of reading out data from a memory array, a programming mode of writing data to the memory array, an erasing mode of erasing data from the memory array and a second reading mode of reading out data not stored in the memory array, in accordance with an input of control command and for performing a predetermined process in the set operational mode.
2. Description of Related Art
As electrically rewritable non-volatile semiconductor memory devices, flash memories are known. In the flash memories, data writing operation to a memory array is carried out by means of a data writing (programming) command. In addition, erasing operation of data written to the memory array is carried out by means of an erasing command, whereby all the memory cells of the memory array simultaneously turn into an erasing status in a block unit.
For this reason, in order to carrying out the reading operation, the writing (programming) operation, the erasing operation in a block unit (or in a sector unit), etc. on the flash memory, it is necessary to first allow the flash memory to read out control commands corresponding to each operation, and then to allow a command condition decoding circuit to decode the operation details. In the flash memory, in order to maintain a data maintenance characteristic with a high quality, the above writing operation and erasing operation are controlled by a writing/erasing control circuit in accordance with complex writing and erasing algorithms. Further, since processing statuses such as start and end of the writing operation and the erasing operation are stored in a status register, the current processing statuses of the writing/erasing control circuit can be externally confirmed by reading out contents stored in the status register. An example of the control commands for the flash memory is listed in Table 1.
TABLE 1First writing cycleSecond writing cyclecommandsData inputData inputArrayFFH—reading/resetprogramming40HWriting dataBlock erasing20HD0HStatus register70H—readingBlock lock60H01HBlock unlock60HD0RBlock lock-down60H2FH
For example, in the array reading operation, when the flash memory receives a command data “FFH” (here, “H” indicates that the data is a hexadecimal expression) via data terminals (in general, the same data terminals are used for input and output of data), and then both of a chip enable signal CE# and an output enable signal OE# become active (here, “#” in the signal names expediently means that the signals having “#” become active when an input level is a low level), the data reading from the memory array is started. In a predetermined time after the start, the flash memory outputs from the data terminals data stored in an address area specified correspondingly to the input level of an address input terminal in the memory array.
In order to input the respective control commands to the flash memory, codes corresponding to the commands shown in Table 1 are input to the data terminals, and both of the chip enable signal CE# and a write enable signal WE# are made to be active.
FIG. 10A is a cross-sectional view schematically illustrating a sectional structure of a memory cell transistor constituting one memory cell in the flash memory. The memory cell transistor of FIG. 10A is formed on a surface region of, for example, a p type semiconductor substrate (or well). The memory cell transistor comprises a source S and a drain D into which n type impurities are injected, a floating gate FG formed on a channel region between the source S and the drain D with a gate insulating film therebetween, and a control gate CG formed on the floating gate FG with an interlayer insulating film therebetween. The floating gate FG is surrounded with an insulating film, and is in an electrical floating status. FIG. 10B is an equivalent circuit diagram of the memory cell transistor shown in FIG. 10A.
While not shown, the control gate CG is connected to a word line WL, and is driven by a word line driving circuit (a row decoder). Further, the drain D is connected to a bit line BL, is driven by a bit line driving circuit (a column decoder) and a sense amplifying circuit (a sense circuit), whereby potential of the bit line is amplified by the sense amplifier to read out data stored in the memory cell. The source S is coupled to a source line driving circuit through a source line.
In the flash memory, such memory cells are arranged in an array shape, each row of memory cells is connected to a corresponding word line WL, and each column of memory cells is connected to a corresponding bit line BL, thereby forming a memory cell array. Writing, erasing and reading of data on the memory cell shown in FIG. 10 are performed as follows.
In writing data, a high voltage Vpp of about 12V is applied to the control gate CG through the word line WL, a voltage of about 6V is applied to the drain D through the bit line BL, and a ground potential is applied to the source S from the source line driving circuit. In this status, a current flows from the drain D to the source S through the channel region. Electric charges in the current from the drain D is excited by means of a high electric field formed around the drain D, and thus hot electrons are generated. The hot electrons cause an avalanche breakdown, and thus a-large amount of hot electrons are serially generated. The hot electrons generated due to the avalanche breakdown are accelerated toward the floating gate FG by means of a high voltage applied to the control gate CG, and are injected into and caught by the floating gate FG. In a status where electrons are caught by the floating gate FG, a threshold voltage Vth of the memory cell transistor is shifted in a positive direction (that is, data “0” is stored).
In erasing data, the ground potential is applied to the control gate CG, the high voltage Vpp of about 12V is applied to the source S from a source potential generating circuit, and the drain D is in a floating status. In this status, electrons are extracted to the source S from the floating gate FG through the gate insulating film (which is a very thin tunnel insulating film) by means of a tunneling effect. In the status where the electrons are extracted from the floating gate FG, the threshold voltage Vth of the memory cell transistor is shifted in a negative direction (that is, data “1” is stored). As described above, the memory cell memorizes data “0” or “1” in accordance with the amount of electrons existing in the floating gate FG. This erasing operation is carried out in a block unit, where the memory array is divided into a plurality of blocks (all the data may be erased in a bundle from the whole memory array, depending upon erasing mechanisms or sizes of the memory arrays).
After turn-on of power or after restoration from reset operation, the flash memory is in an operational mode (an array reading mode) of reading out data of the memory cell shown in FIG. 10. For this reason, in a computer system storing program codes, etc. in the flash memory, a CPU can read out the corresponding program code suitably for the situations. However, when a status register reading command is generated, the flash memory is in a status register reading mode, and thus data from the status register, not data from the memory array, are output. As a result, the CPU having been reading out data (programs or data, etc.) from the flash memory reads out erroneous data. In this way, when the status register reading mode is erroneously set, the computer system (CPU) starts runaway (erroneous operation).
On the other hand, when an erasing command or a programming command is issued to the flash memory, a writing/erasing control circuit starts the erasing operation or the writing operation. When the writing/erasing control circuit starts the erasing operation or the writing operation, the flash memory is automatically set to the status register reading mode. This is because the intentional input of the status register reading command is not necessary for confirmation of the processing statuses in the programming mode or the erasing mode. Therefore, there is no problem in the normal operation, but when the programming mode or the erasing mode is erroneously set due to noises, etc., the flash memory may output erroneous data, and the computer system (CPU) reading out the erroneous data may thus start the runaway (erroneous operation).
Here, a bit 7 (eighth bit) of bits of the status register is “1” (Ready) when the writing/erasing control circuit is in a wait status, for example, in the array reading mode, etc. When the writing/erasing control circuit starts controlling the erasing operation or the writing operation, the bit 7 of the status register turns into “0” (Busy), and when the erasing operation or the writing operation is completed, the bit 7 is restored to “1” (Ready), thereby notifying completion of the erasing operation or the writing operation.
In order to restore the operational mode from the status register reading mode to the operational mode (array reading mode) of reading out data from the memory array, the array reading command FFH should be issued. Thereafter, the flash memory can read out data from the memory array.
FIG. 11 illustrates an arrangement example of terminals of the flash memory. FIG. 11 shows an example of a product in which the flash memory is sealed with a 48-pin TSOP package.
As a case where the status register reading mode is set in addition to the above description, when a VPP terminal (an input terminal of writing/erasing high voltage) turns into a low level, the writing operation or the erasing operation is inhibited, but the flash memory may be set to the status register reading mode. In addition, when a WP# terminal (an input terminal of a write protecting control signal) turns into a low level, the data writing operation and the data erasing operation on a specific block of the memory array are inhibited, but the flash memory may be set to the status register reading mode.
In addition, methods of preventing the writing operation and the erasing operation on the specific block are disclosed in Japanese Patent Unexamined Publication JP-A 9-69066 (1997) (Patent Document 1) and Japanese Patent Unexamined Publication JP-A 2002-366436 (2000) (Patent Document 2). Patent Document 1 discloses a method in which a protection status setting unit is provided in each block, so that when a block requiring a protection status is set by the protection status setting unit, the writing/erasing operation on the corresponding block is prevented, and when the protection status is released by the protection status setting unit, the writing/erasing operation is enabled. Patent Document 2 discloses a method in which in a circuit or system having a non-volatile memory which is rewritable every block, when the writing operation is carried out on a block specified by a protection area specifying unit, only a high level signal is supplied to the WE# terminal, and on the contrary, when the writing operation is carried out on a block not specified by the protection area specifying unit, an active signal (a low level) is supplied to the WE# terminal, thereby writing commands and data.
However, in the above two methods, when the WE# signal is fixed to a high level, the rewriting operation is prevented and only the reading operation is enabled by the protection area specifying unit. Therefore, if a situation (erroneous writing operation) where the WE# signal erroneously turns into the active level (a low level) is caused due to system noises, etc., that is, if an erroneous control command is received, there is a possibility that restoration from the status register reading mode could not be performed.
When control commands (for example, 20H, 40H, 70H) other than FFH is erroneously input to the flash memory due to system noises, etc. unexpectedly generated in turn-on of power or electrical connection, the flash memory is automatically set to the status register reading mode. Thereafter, when both of the chip enable signal CE# and the output enable signal OE# become active, the reading operation on the status register is started, and in a predetermined time after the starting, the flash memory outputs values of the status register to the data terminal.
Since the flash memory does not output data (program code, etc.) stored in an address area specified correspondingly to an input level of an address input terminal in the memory array, the CPU having been reading out the data starts the runaway (erroneous operation). In the circuit or system having a non-volatile memory which is rewritable in every block, which is disclosed in Patent Document 2, when the writing operation is carried out on a block specified by a protection area specifying unit, the rewriting operation is prevented and only the reading operation is enabled, so that only a high level signal is supplied to the WE# terminal, and on the contrary, when the writing operation is carried out on a block not specified by the protection area specifying unit, an active signal (a low level signal) is supplied to the WE# terminal, thereby reading out the control commands and the stored data.
In this case, if the signal level of the WE# signal is changed due to system noises, etc. unexpectedly generated in turn-on of power or electrical connection and thus the flash memory erroneously reads out the control commands (for example, 20H, 40H, 70H) other than FFH (array reading/reset), the flash memory is automatically set to the status register reading mode. When the wring operation is carried on a block specified by the protection area specifying unit, only a high level signal is normally supplied to the WE# terminal, so that the flash memory may not release the status register reading mode.